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      Job Description:

      This position will be responsible for the board enablement and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to be working closely with SoC design/verification, platform design and product team to work out the total solution from the bare-metal, device driver toautomation validation framework.

      Main responsibilities include:

      1、Develop the bare metal software to bring up and validate the SiEngine automotive SoC.

      2、 Develop the software to enable and validate the development boards.

      3、 Build the automation validation framework.

      4、 Develop the tools for the SoC and board manufacture.

      5、 Provide the debug tools for the SiEngine automotive SoC.

      Job Requirements:

      1、B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

      2、 5+ years of software development in automotive, embedded system or mobile.

      3、 At least 2-years of experience in writing low-level software that interacts directly with hardware.

      4、 Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection).

      5、 Experience in driver development or experience in Linux driver development is a plus.

      6、Familiar with bootloader, Linux and any RTOS.

      7、 Familiar with board design and schematic.

      8、 Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.

      9、 Experience in LSIO such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.

      10、 Experience in LSIO such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.

      11、 Familiar with Git/Gerrit source code management tool.

      12、 Familiar with Git/Gerrit source code management tool.

      Job Description:

      1、Plan the EDA tool licensing, installation, manage disk/machines requirements, Library & IP release.

      2、Build and enhance the design flow infrastructure of Soc design to improve design efficiency and quality.

      3、Setup design environment related with Cadence, Synopsys, Mentor and other EDA tools.

      4、Develop infrastructure for flow regression, automation flow and smart diagnosis solutions.

      5、Work with design engineers to debug design/EDA environment issues.

      Job Requirements:

      1、2+ years of hand-on experience in EDA/CAD related field.

      2、 Experienced with ASIC design flow.

      3、 Hand on experience on C++/Java, Perl, Python, TCL, shell, Makefile.

      4、 Experience with data collection, analysis and reporting techniques.

      5、 Strong analytical problem solving, team work and communication skills.

      6、Proactive and self-motivated is must.

      Job Description:

      1、Plan the EDA tool licensing, installation, manage disk/machines requirements, Library & IP release.

      2、Build and enhance the design flow infrastructure of Soc design to improve design efficiency and quality.

      3、Setup design environment related with Cadence, Synopsys, Mentor and other EDA tools.

      4、Develop infrastructure for flow regression, automation flow and smart diagnosis solutions.

      5、Work with design engineers to debug design/EDA environment issues.

      Job Requirements:

      1、2+ years of hand-on experience in EDA/CAD related field.

      2、 Experienced with ASIC design flow.

      3、 Hand on experience on C++/Java, Perl, Python, TCL, shell, Makefile.

      4、 Experience with data collection, analysis and reporting techniques.

      5、 Strong analytical problem solving, team work and communication skills.

      6、Proactive and self-motivated is must.

      Job Description:

      1、Plan the EDA tool licensing, installation, manage disk/machines requirements, Library & IP release.

      2、Build and enhance the design flow infrastructure of Soc design to improve design efficiency and quality.

      3、Setup design environment related with Cadence, Synopsys, Mentor and other EDA tools.

      4、Develop infrastructure for flow regression, automation flow and smart diagnosis solutions.

      5、Work with design engineers to debug design/EDA environment issues.

      Job Requirements:

      1、2+ years of hand-on experience in EDA/CAD related field.

      2、 Experienced with ASIC design flow.

      3、 Hand on experience on C++/Java, Perl, Python, TCL, shell, Makefile.

      4、 Experience with data collection, analysis and reporting techniques.

      5、 Strong analytical problem solving, team work and communication skills.

      6、Proactive and self-motivated is must.

      Job Description:

      1、As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to.

      2、Deeply understand system level requirements and IP features, create sub-system design.

      3、Deeply understand system level requirements and IP features, create sub-system design.

      4、Assist with chip bring up and perform silicon functional/performance validation.

      5、Assist with implementation team on netlist release, P&R suggestion and timing tuning.

      Job Requirements:

      1、 Degree in electrical engineering, computer engineering or related technical fields.

      2、 Good knowledge of Verilog/SystemVerilog.

      3、 Hand on experience on any of these tasks: Lint/CDC check, SDC/UPF generation, Synthesis, Formal.

      4、 A high-level of self-motivation and a proactive approach to solving problems.

      Job Requirements:

      1、 Hands on experience on Subsystem level design.

      2、 Familiar with Vendor’s PCIE controller and Phy, both function and test mode.

      3、 Familiar with AMBA spec and SOC architecture.

      4、 Familiar with frontend ASIC design methodology/flow.

      5、 Experience of Low power design.

      6、 Experience of follow IP is a strong plus: PCIE/UFS/USB/eMMC/GPU/ISP/MIPI/VPU/NPU/ DisplayPort/NoC/DDR/Ethernet/ AMBA AXI/AHB/APB/ GIC/SMMU/CoreSight.

      Job Description:

      1、As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to.

      2、Deeply understand system level requirements and IP features, create sub-system design.

      3、Deeply understand system level requirements and IP features, create sub-system design.

      4、Assist with chip bring up and perform silicon functional/performance validation.

      5、Assist with implementation team on netlist release, P&R suggestion and timing tuning.

      Job Requirements:

      1、 Degree in electrical engineering, computer engineering or related technical fields.

      2、 Good knowledge of Verilog/SystemVerilog.

      3、 Hand on experience on any of these tasks: Lint/CDC check, SDC/UPF generation, Synthesis, Formal.

      4、 A high-level of self-motivation and a proactive approach to solving problems.

      Job Requirements:

      1、 Hands on experience on Subsystem level design.

      2、 Familiar with Vendor’s PCIE controller and Phy, both function and test mode.

      3、 Familiar with AMBA spec and SOC architecture.

      4、 Familiar with frontend ASIC design methodology/flow.

      5、 Experience of Low power design.

      6、 Experience of follow IP is a strong plus: PCIE/UFS/USB/eMMC/GPU/ISP/MIPI/VPU/NPU/ DisplayPort/NoC/DDR/Ethernet/ AMBA AXI/AHB/APB/ GIC/SMMU/CoreSight.

      Job Description:

      1、As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to.

      2、Deeply understand system level requirements and IP features, create sub-system design.

      3、Deeply understand system level requirements and IP features, create sub-system design.

      4、Assist with chip bring up and perform silicon functional/performance validation.

      5、Assist with implementation team on netlist release, P&R suggestion and timing tuning.

      Job Requirements:

      1、 Degree in electrical engineering, computer engineering or related technical fields.

      2、 Good knowledge of Verilog/SystemVerilog.

      3、 Hand on experience on any of these tasks: Lint/CDC check, SDC/UPF generation, Synthesis, Formal.

      4、 A high-level of self-motivation and a proactive approach to solving problems.

      Job Requirements:

      1、 Hands on experience on Subsystem level design.

      2、 Familiar with Vendor’s PCIE controller and Phy, both function and test mode.

      3、 Familiar with AMBA spec and SOC architecture.

      4、 Familiar with frontend ASIC design methodology/flow.

      5、 Experience of Low power design.

      6、 Experience of follow IP is a strong plus: PCIE/UFS/USB/eMMC/GPU/ISP/MIPI/VPU/NPU/ DisplayPort/NoC/DDR/Ethernet/ AMBA AXI/AHB/APB/ GIC/SMMU/CoreSight.

      Job Description:

      As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

      1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.

      2、Block level dft drc check & fix it in RTL/Netlist level.

      3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.

      4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.

      Job Requirements:

      1、Hand on experience of SoC DFT implementation, Scan Compression logic/MBIST logic/Boundary scan chain insertion, pattern bring up and diagnose.

      2、 Expertise with Mentor/Synopsys DFT tools.

      3、 Expertise with DFT advisor tools.

      4、 Experience in MBIST/SCAN/ATPG Pattern simulation and debug on RTL & Netlist.

      5、 A high-level of self-motivation and a proactive approach to solving problems.

      Job Description:

      As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

      1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.

      2、Block level dft drc check & fix it in RTL/Netlist level.

      3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.

      4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.

      Job Requirements:

      1、Hand on experience of SoC DFT implementation, Scan Compression logic/MBIST logic/Boundary scan chain insertion, pattern bring up and diagnose.

      2、 Expertise with Mentor/Synopsys DFT tools.

      3、 Expertise with DFT advisor tools.

      4、 Experience in MBIST/SCAN/ATPG Pattern simulation and debug on RTL & Netlist.

      5、 A high-level of self-motivation and a proactive approach to solving problems.

      Job Description:

      As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

      1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.

      2、Block level dft drc check & fix it in RTL/Netlist level.

      3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.

      4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.

      Job Requirements:

      1、Hand on experience of SoC DFT implementation, Scan Compression logic/MBIST logic/Boundary scan chain insertion, pattern bring up and diagnose.

      2、 Expertise with Mentor/Synopsys DFT tools.

      3、 Expertise with DFT advisor tools.

      4、 Experience in MBIST/SCAN/ATPG Pattern simulation and debug on RTL & Netlist.

      5、 A high-level of self-motivation and a proactive approach to solving problems.

      Job Description:

      1、SOC Design-For-Debug &Test methodology and micro architecture development.

      2、ARM CoreSight micro architecture development and debug subsystem design and verification.

      3、High performance and real-time cross-trigger engine design and verification for multi-core SOC.

      4、Test-controller design and verification for PLL, MIPI, PCIE, USB3, DDR Debug and test.

      5、Co-work with DFT team for SOC debug/test logic design and verification.

      Job Requirements:

      1、 Hand on experience of logic design.

      2、 Be familiar with ARM CoreSight architecture.

      3、 Be familiar with IEEE1149.1, IEEE 1149.6, IEEE 1500.

      4、 Be familiar with Frontend design & implementation flow,Such as:Lint,CDC check,logic synthesis,formal;Be familiar with related EDA tools.

      5、 Experience on analog IP testing is a plus.

      6、 Familiar with unix/linux and scripts (tcl, perl, makefile etc.).

      7、 Teamwork, A high-level of self-motivation and a proactive approach to solving problems.

      Job Description:

      1、SOC Design-For-Debug &Test methodology and micro architecture development.

      2、ARM CoreSight micro architecture development and debug subsystem design and verification.

      3、High performance and real-time cross-trigger engine design and verification for multi-core SOC.

      4、Test-controller design and verification for PLL, MIPI, PCIE, USB3, DDR Debug and test.

      5、Co-work with DFT team for SOC debug/test logic design and verification.

      Job Requirements:

      1、 Hand on experience of logic design.

      2、 Be familiar with ARM CoreSight architecture.

      3、 Be familiar with IEEE1149.1, IEEE 1149.6, IEEE 1500.

      4、 Be familiar with Frontend design & implementation flow,Such as:Lint,CDC check,logic synthesis,formal;Be familiar with related EDA tools.

      5、 Experience on analog IP testing is a plus.

      6、 Familiar with unix/linux and scripts (tcl, perl, makefile etc.).

      7、 Teamwork, A high-level of self-motivation and a proactive approach to solving problems.

      Job Description:

      1、SOC Design-For-Debug &Test methodology and micro architecture development.

      2、ARM CoreSight micro architecture development and debug subsystem design and verification.

      3、High performance and real-time cross-trigger engine design and verification for multi-core SOC.

      4、Test-controller design and verification for PLL, MIPI, PCIE, USB3, DDR Debug and test.

      5、Co-work with DFT team for SOC debug/test logic design and verification.

      Job Requirements:

      1、 Hand on experience of logic design.

      2、 Be familiar with ARM CoreSight architecture.

      3、 Be familiar with IEEE1149.1, IEEE 1149.6, IEEE 1500.

      4、 Be familiar with Frontend design & implementation flow,Such as:Lint,CDC check,logic synthesis,formal;Be familiar with related EDA tools.

      5、 Experience on analog IP testing is a plus.

      6、 Familiar with unix/linux and scripts (tcl, perl, makefile etc.).

      7、 Teamwork, A high-level of self-motivation and a proactive approach to solving problems.

      Job Description:

      As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

      1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

      2、Bring up the virtual platform and analysis the performance and power simulation result.

      3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

      4、Work out the highly configurable work load model for the various components in various scenarios.

      5、Work out the SoC use case and performance goal in system level with help from product engineer.

      6、Assist design engineer to work out the ASIC micro-architecture.

      7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

      Job Requirements:

      1、 Degree in electrical engineering, computer engineering or related technical fields.

      2、 Good knowledge of C++/SystemC modeling.

      3、 Good knowledge on the Verilog and SystemVerilog.

      4、 A high-level of self-motivation and a proactive approach to solving problems.

      Solid knowledge in one of the following areas is a plus:

      1、 Strong experience of high level modeling or software development with C++.

      2、 experience of the ASIC design or verification.

      3、 Familiar with AMBA AXI/AHB/APB spec.

      4、 experience of GPU/VPU/DPU.

      5、 experience of PCIE/USB/Ethernet/UFS/eMMC.

      6、 Experience of low power design and power analysis.

      7、 Experience of complex SoC modeling.

      Job Description:

      As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

      1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

      2、Bring up the virtual platform and analysis the performance and power simulation result.

      3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

      4、Work out the highly configurable work load model for the various components in various scenarios.

      5、Work out the SoC use case and performance goal in system level with help from product engineer.

      6、Assist design engineer to work out the ASIC micro-architecture.

      7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

      Job Requirements:

      1、 Degree in electrical engineering, computer engineering or related technical fields.

      2、 Good knowledge of C++/SystemC modeling.

      3、 Good knowledge on the Verilog and SystemVerilog.

      4、 A high-level of self-motivation and a proactive approach to solving problems.

      Solid knowledge in one of the following areas is a plus:

      1、 Strong experience of high level modeling or software development with C++.

      2、 experience of the ASIC design or verification.

      3、 Familiar with AMBA AXI/AHB/APB spec.

      4、 experience of GPU/VPU/DPU.

      5、 experience of PCIE/USB/Ethernet/UFS/eMMC.

      6、 Experience of low power design and power analysis.

      7、 Experience of complex SoC modeling.

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